Integrated chips are formed by operating upon a semiconductor substrate with a plurality of integrated chip (IC) fabrication processes. In general, the IC fabrication processes used to form an integrated chip are separated into front-end-of-the-line (FEOL) processes and back-end-of-the-line (BEOL) processes. During FEOL processes, one or more transistor devices may be formed onto a semiconductor substrate. During BEOL processes, one or more metallization layers are formed within a dielectric material. The one or more metallization layers connect the one or more transistor devices to external (i.e., off-chip) components.
Typically, between the completion of FEOL processes and the commencement of BEOL processes, a dielectric layer is deposited between adjacent transistor devices (e.g., between adjacent gate structures). This dielectric layer, vertically positioned between the transistor devices and the metallization layers, is known as a pre-metal dielectric (PMD) layer.